DDR overview

AN3132

8/24

Doc ID 16955 Rev 1

2.1.2

Power supply differences

DDR2 operates at 1.8 V. This is a 28% reduction compared to DDR1, which combined with

power saving features such as smaller page sizes and an active power down mode results

in power consumption advantages.

2.1.3

Other feature differences

DDR2 has also some other new features like on die termination (ODT). Around the memory

slots on a DDR1-supporting motherboard, there can be termination resistors, which are

used to eliminate excessive signal noise. For DDR2 modules, the termination resistors are

built into the chip, which are far closer to the source of the noise. This ODT feature can

reduce interference within the chip, thus guaranteeing the stability and reliability of DDR2

memory when working under high frequencies.

calibration (OCD), which increases signal integrity and system timing margin as well.

2.2

Addressing

Once configured, you do not need to to worry about the DDR protocol; you can access the

DDR by directly accessing the memory address. In SPEAr600, DDR is mapped from

0x0000_0000 to 0x3FFF_FFFF: that means that an addressable space of 1 GB is dedicated

to the external DRAM. In this way you can address, using all the 30 address bits, up to 2 x 4

Gb memory chips. Only 256 Mb x 16 cuts are possible because of the presence of only 14

address lines, DDR_MEM_ADDR [14:0]. In this case, the use of the bits is divided in the

following way:

●

10 bits for column address

●

3 bits for bank address

●

15 bits for row address

In the user address, bit 0 is used to select the width of the datapath. It is fixed to ‘0’ if the

datapath is 16 bit and if the datapath is 8 bit, it is fixed to ‘1’.

So in this case:

●

User_address [0] = datapath;

●

User_address [10:1] = column address;

●

User_address [13:11] = bank address;

●

User_address [28:14] = row address;

●

User_address [29] = chip select;

Regardless of the memory cut selected, the CPU always sees a contiguous addressable

space. For this reason, the memory controller always shifts the memory address parts (row,

bank and column) in the user address according to the physical memory cut attached and

its configuration.