DDR programming in Spear600

AN3132

10/24

Doc ID 16955 Rev 1

3

DDR programming in Spear600

In the SPEAr600 LSP (Linux support package), the memory controller is programmed in a

small piece of firmware executed just after boot ROM code and named “Xloader”. The

standard Xloader provided by STMicroelectronics is coded for the DDR2 device installed on

the ST SPEAr600 evaluation board. The memory part available on ST’s evaluation board is

either an mt47H64M16_3 1-Gbit or an mt47H32M16 viz. 512-Mbit capacity DDR2 device.

You need to:

●

Change the setting of the memory controller in case of different vendor /different

memory sizes. Refer to Section 4: Configuring SPEAr MPMC for a specific DDR

memory part for the procedure to follow.

●

Fine tune the DLL to find the best settings of the MPMC in the your application board,

as explained in Section 5: DDR controller delay lines tuning.

The objective of the next two sections is to provide all the information you need to customize

the “general purpose” MPMC settings provided by ST, modifying them to match your

application requirements.