AN3132

Pad descriptions and configurations

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Pad descriptions and configurations

To ensure correct behavior of the memory controller in any application, you need to properly

configure the various pads that interface the DDR memory.

The following table contains the complete list of the SPEAr600 pads involved with the use of

DDR.

Except for some reference pads, all the pads can be divided into two main groups on the

basis of the nature of the digital cell present in the pad:

●

Data cell (BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG)

●

Clock cell (BDCLKDDRSCARUDQP_1V8_2V5_NORES_STAG)

The figures below show the data cell and clock cell architecture.

Table 4.

SPEAr600 memory controller pads

Signal

Pad type

Direction

DDR_MEM_COMP2V5_REXT ANA_2V5_STAG

DDR_MEM_COMP1V8_REXT ANA_1V8_STAG

DDR_MEM_ADDR[14:0]

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_RAS

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_CAS

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_WE

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_CS[1:0]

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_BA[2:0]

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_CLKEN

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_GATE_OPEN[1:0] BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

INOUT

DDR_MEM_ODT[1:0]

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_DM[1:0]

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

OUT

DDR_MEM_DQS[1:0]

BDCLKDDRSCARUDQP_1V8_2V5_NORES_STAG

INOUT

nDDR_MEM_DQS[1:0]

BDCLKDDRSCARUDQP_1V8_2V5_NORES_STAG

INOUT

DDR_MEM_DQ[15:0]

BDPROGDDRSCARUDQP_VDDE/GNDE_1V8_2V5_NORES_STAG

INOUT

DDR_MEM_CLKP

BDCLKDDRSCARUDQP_1V8_2V5_NORES_STAG

OUT

DDR_MEM_CLKN

BDCLKDDRSCARUDQP_1V8_2V5_NORES_STAG

OUT

DDR_MEM_VREF

VREFSSTL_1V8_STAG

DDR2_EN

BD2TARUQP_3V3_STAG

IN