AN3961 datasheet(29/46 Pages) STMICROELECTRONICS

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AN3961

Hardware layout and configuration

Figure 17. STHV748 single channel block diagram

The STHV748 output waveforms can be displayed directly for each channel Ch A/B/C/D

using an oscilloscope by connecting the scope probe to the J22, J23, J25, and J26 BNC

connectors. Also, the user can select whether or not to connect the on-board equivalent

load, a 270 pF, 200 V capacitor paralleled with a 100

Ω, 2 W resistor (through J20, J21, J27,

J28). A coaxial cable can also be used to easily connect the user’s transducer. Additionally,

four more low voltage outputs are available to receive the echo transduced signal coming

from the piezo-element through HVR_SW (J16, J17, J29, J30).

The main issues in this PCB design are the capacitance values, to ensure good filtering and

an effective decoupling between the low voltage inputs (IN1, IN2, IN3, IN4, and EN for each

channel) and the HV switching signals (XDCR, HVOUT, etc.,) which is ensured by the layer

separation used.

3.6

Operating supply conditions

Table 15. DC working supply conditions

Operating supply voltages

Symbol

Parameter

Min.

Typ.

Max.

Value

VDDP

Positive supply voltage

2.7

3.6

VDDM

Negative supply voltage

-2.7

-3

-3.6

VDD

Positive logic voltage

2.4

Min (3.6,VDDP+0.3)

HVP0

TX0 high voltage positive supply

HVP1

TX1 high voltage positive supply

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