Running the demonstrations

STR91x demonstration software

12/20

2.2

Clock sources

2.2.1

Clock control

The STR91x internal clocks are derived from an on-board 25 MHz crystal source.

In this demo application, the system clock is configured as follow:

●

HCLK frequency is set to 96 MHz

●

FMICLK frequency is set to 96 MHz

●

PCLK is set to 48 MHz

●

USB clock (CK_USB) is set to 48 MHz (internal clock)

Only the RTC is clocked by a 32 kHz external oscillator.

Figure 4.

Clock control

1/2

1/2

(1,2,4)

AHBDIV

RCLKDIV

(1,2,4,8,16,1024)

RCLK

HCLK

(1,2,4,8)

APBDIV

Peripheral

Clock

Gating

HCLK

to AHB

peripherals

PCLK

Peripheral

Clock

Gating

PCLK

to APB

peripherals

X1_CPU

X2_CPU

MII_PHYCLK

X1_RTC

X2_RTC

MAIN

OSC

OSC

RTC

PHYSEL

PLL

EXTCLK_T0T1

EXTCLK_T2T3

USB_CLK48M

to USB block

BRCLK

FMICLK

to Flash Memory

Baud rate clock to UARTs

Peripheral

Clock

Gating

FMICLK

Interface

to TIM0 & TIM1

Peripheral

Clock

Gating

TIM01CLK

to TIM2 & TIM3

Peripheral

Clock

Gating

TIM23CLK

Peripheral

Clock

Gating

48 MHz USBCLK

16-bit prescaler

1/2

MCLKSEL

25 MHz

4 to 25 MHz

32.768

to CPU

CPUCLK

Special interrupt

mode control

to RTC

to WDG (software

selectable in WDG

register)

kHz

16-bit prescaler