UPD70F3003A datasheet(26/44 Pages) NEC

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µPD70F3003A, 70F3025A

Data Sheet U13189EJ3V0DS00

(7) Bus hold timing (1/2)

Parameter

Symbol

Condition

25 MHz Model

33 MHz Model

Unit

MIN.

MAX.

MIN.

MAX.

HLDRQ setup time (vs. CLKOUT

↓) <54> tSHOK

HLDRQ hold time (vs. CLKOUT

↓) <55> tHKHQ

CLKOUT

↑→ HLDAK delay time

<56>

tDKHA

HLDRQ width, high

<57>

tWHQH

T + 10

HLDAK width, low

<58>

tWHAL

–40

°C ≤ TA ≤ +70°C

T – 10

°C < TA ≤ 85°C

T – 12

CLKOUT

↑ → Bus float delay time

<59>

tDKF

HLDAK

↑→ bus output delay time <60> tDHAC

–3

HLDRQ

↓→ HLDAK ↓ delay time

<61>

tDHQHA1

(2 n + 7.5) T + 20

HLDRQ

↑→ HLDAK ↑ delay time

<62>

tDHQHA2

0.5 T

1.5 T + 20

0.5 T

1.5 T + 20

Remarks 1. T = tCYK

2. n indicates the number of wait clocks inserted in the bus cycle. The sampling timing differs when

the programmable wait state is inserted.

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