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UPD70F3003A Datasheet(PDF) 31 Page - NEC |
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UPD70F3003A Datasheet(HTML) 31 Page - NEC |
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31 / 44 page ![]() µPD70F3003A, 70F3025A 31 Data Sheet U13189EJ3V0DS00 (9) CSI timing (2/2) (ii) CSI3 timing Parameter Symbol Condition 25 MHz Model 33 MHz Model Unit MIN. MAX. MIN. MAX. SCK3 cycle <67> tCYSK4 Input 500 500 ns SCK3 width, high <68> tWSKH4 Input 180 180 ns SCK3 width, low <69> tWSKL4 Input 180 180 ns SI3 setup time (vs. SCK3 ↑) <70> tSSISK4 100 100 ns SI3 hold time (vs. SCK3 ↑) <71> tHSKSI4 50 50 ns SO3 output delay time (vs. SCK3 ↓) <72> tDSKSO4 RL = 1.5 k Ω 150 150 ns SO3 output hold time (vs. SCK3 ↑) <73> tHSKSO4 CL = 50 pF tWSKH4 tWSKH4 ns Remark RL and CL are the load resistance and load capacitance respectively of the SCK3 and SO3 output lines. SCKn (I/O) SIn (input) SOn (output) < 67 > < 69 > < 68 > < 70 > < 71 > < 72 > < 73 > Input data Output data Remark 1. The broken line indicates the high-impedance state. 2. n = 0-3 |
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