Gate to cathode capacitor, impact on dV/dt immunity

AN4030

8/15

Doc ID 022635 Rev 1

1.4

Behavior of Triacs to EFT (electrical fast transient)

To compare immunity between several Triacs (snubberless and logic level) with and without

gate to cathode capacitor, tests have been carried out in the following conditions (see

Figure 8):

●

An X2 1nF capacitor is connected at line input.

●

The PCB is 10 cm above the reference plane.

●

The Triac A2 terminal is linked to a 25 W light bulb (resistive loads are chosen in order

to reduce dI/dt rates in case of firing).

●

The gate could be left open, or connected to A1 terminal through an external gate to

cathode capacitor or connected to A1 through a 100

Ω R

cathode capacitor.

●

No snubber circuits are added across the Triacs.

●

Ambient temperature: 25 °C.

●

The burst generator is programmed as required in the IEC 61000-4-4 standard (15 ms

burst duration, 3 Hz burst frequency, 5 kHz spike frequency, one second test duration).

Table 2.

Without gate to cathode

capacitor

With gate to cathode

capacitor (100 nF)

Sample 1

Sample 2

Sample 1

Sample 2

dV/dt

(V/µs)

Direct

2350

1850

2350

1850

Reverse

2750

1950

2750

1950