Peripheral firmware examples description

AN4157

8/24

Doc ID 023629 Rev 1

Each time the push-button is pressed, two signals have been selected and monitored on the

DAC Channels:

●

Escalator waveform (Channel 1) and Sine waveForm (Channel 2).

●

Noise waveform (Channel 1) and Triangle waveform (Channel 2).

Note:

Use the push-button connected to PA0.

Connect PA4 (DAC Channel1) and PA5 (DAC Channel2) pins to an oscilloscope to monitor

the DAC out waves.

3.4

DMA Flash RAM example

3.4.1

Purpose

This example describes how to use a DMA channel to transfer a word data buffer from the

Flash memory to the embedded SRAM memory.

3.4.2

Description

DMA1 Channel1 is configured to transfer the content of a 32-word data buffer, stored in the

Flash memory, to the reception buffer declared in RAM.

●

The start of transfer is triggered by software. DMA1 Channel1 memory-to-memory

transfer is enabled as well as source and destination address incrementing.

●

The transfer is started by setting the Channel enable bit for DMA1 Channel1.

●

At the end of the transfer, a Transfer Complete interrupt is generated since it is enabled.

Once the interrupt is generated, the remaining data to be transferred is read, it must be

equal to 0. The Transfer Complete Interrupt pending bit is then cleared. A comparison

between the source and destination buffers is done to check that all data have been

correctly transferred.

3.5

DMA RAM DAC example

3.5.1

Purpose

This example provides a description of how to use a DMA channel to transfer data buffer

from RAM memory to DAC.

3.5.2

Description

DMA2 channel3 is configured to transfer continuously, word by word, a 32-word buffer to the

dual DAC register DAC_DHR12RD. Both DAC channels conversions are configured to be

triggered by TIM2 TRGO triggers and without noise/triangle wave generation. 12-bit right

data alignment is selected to be able to access DAC_DHR12RD register.

Note:

Connect the oscilloscope to PA04 and PA05.