AN4157

Peripheral firmware examples description

Doc ID 023629 Rev 1

17/24

TIM1 is configured to generate the reference signal used by TIM8 on Channel1:

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TIM1 generates a PWM signal with a frequency equal to 1.4560 kHz.

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TIM1 is used as master for TIM8: TIM1 update event resets TIM8 counter to

synchronize the reference signal (TIM1_CH1) and the shifted signal (TIM8_CH2).

TIM1 and TIM8 input clock (TIM18CLK) is set to APB2 clock (PCLK2). TIM1 and TIM8

signals are at frequency of (SystemCoreClock / (Period + 1)).

TIM8 generates a signal with the following characteristics:

Pulse length = (TIM8_CCR1 + TIM8_CCR2) / TIM8_CLK

Phase shift = TIM8_CCR1/TIM8_CLK

where TIM8_CLK = (SystemCoreClock / (Period + 1)), as the prescaler is equal to zero.

Connect the following pins to an oscilloscope to monitor the different waveforms:

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PA08 (TIM1_CH1)

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PB08 (TIM8_CH2)

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PB06 (TIM8_CH1)

Note:

The shift is measured using the TIM1_CH1 as reference signal.

3.20

TIM combined example

3.20.1

Purpose

This example provides a short description of how to configure the TIM1 peripheral to

generate 3 PWM combined signals with TIM1 Channel5.

3.20.2

Description

The TIM1 input clock (TIM1CLK) with prescaler 0 is set to APB2 clock (PCLK2), which is

equal to system clock (SystemCoreClock).

SystemCoreClock is set to 72 MHz for STM32F30x or STM32F31x devices.

The objective is to generate 3 combined PWM signal at 8.78 kHz (in center aligned mode):

TIM1_Period = (SystemCoreClock / (8.78*2)) - 1

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The channel 1 duty cycle is set to 50%

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The channel 2 duty cycle is set to 37.5%

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The channel 3 duty cycle is set to 25%

The Timer pulse is calculated as follows:

ChannelxPulse = DutyCycle * (TIM1_Period - 1) / 100

The channel 5 is used in PWM2 mode with duty cycle set to 6.22%

The 3 resulting signals are made of an AND logical combination of two reference PWMs:

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Channel 1 and Channel 5

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Channel 2 and Channel 5

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Channel 3 and Channel 5