AN4472 datasheet(10/44 Pages) STMICROELECTRONICS

10 / 44 page

Hardware layout and configuration

AN4472

10/44

DocID026198 Rev 1

The FPGA state machine can be also controlled by an external digital device through the

FPGA USER I/O connector (J7); see Table 28 for the relative naming and pin-out

positioning.

To enable remote control of the board through an external device, the REMOTE_ENABLE

pin must be set high. The waveform program can be selected by setting the PROG<3:0>

port. If an uninstalled program is selected, the ERROR output signal goes high. Also, the

idle state can be selected through the IDLE_SEL<1:0> port. If remote control is enabled, the

Program, Start and Stop buttons are disabled.

A waveform program can be started by means of the REMOTE_START signal (active high)

and stopped by setting high the REMOTE_STOP signal. Either the FPGA reset (SW5) or

REMOTE_RESET signal can be used to reset the FPGA.

Some internal FPGA control signals can be monitored through the FPGA USER I/O

connector (regardless of whether remote control is enabled or disabled). Figure 4 and

Figure 5 show the expected behavior of these timing control signals.

Figure 4. FPGA timing control signals (beginning of cycle n)

Figure 5. FPGA timing control signals (ending of cycle n)

Red

ERROR

An error has occurred during FPGA state machine

execution.

D23

Green

DONE

The FPGA has been successfully configured.

D6-D21

Yellow

PROG 0-15

The corresponding program is selected

Table 7. FPGA LED (continued)

Color

Name

Description

AN4472 Datasheet(PDF) 10 Page - STMicroelectronics