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AN4472 Datasheet(PDF) 22 Page - STMicroelectronics |
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AN4472 Datasheet(HTML) 22 Page - STMicroelectronics |
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22 / 44 page  Hardware layout and configuration AN4472 22/44 DocID026198 Rev 1 Figure 15. Acquisition by Program 5, where C1, C2, C3 and C4 are XDCR_1, XDCR_2, XDCR_3 and XDCR_4 respectively Table 19. State sequence Program 5 XDCR_1 XDCR_2 XDCR_3 XDCR_4 CLAMP 2 µs CLAMP 2 µs CLAMP 2 µs CLAMP 2 µs HVP0 200 ns HVM1 200 ns HVP0 100 ns HVM1 100 ns HVM0 200 ns HVP1 200 ns HVM0 100 ns HVP1 100 ns CLAMP 6 µs CLAMP 6 µs CLAMP 6 µs CLAMP 6 µs HVM0 200 ns HVP1 200 ns HVM0 100 ns HVP0 100 ns HVP0 200 ns HVM1 200 ns HVP0 100 ns HVM0 100 ns CLAMP 291.2 µs CLAMP 291.2 µs CLAMP 291.6 µs CLAMP 291.6 µs |
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