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AN4472 Datasheet(PDF) 32 Page - STMicroelectronics |
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AN4472 Datasheet(HTML) 32 Page - STMicroelectronics |
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32 / 44 page ![]() Connectors AN4472 32/44 DocID026198 Rev 1 4.5 FPGA FPGA USER I/O connector (J7) connector is used for debugging purpose; it allows users to directly interface with FPGA I/Os. Table 28. FPGA USER I/O connector pin out Pin number Description Pin number Description Direction 1 GND 2 CW OUTPUT 3 GND 4 TRIGGER_OUT OUTPUT 5 GND 6 CLKOUT OUTPUT 7 GND 8 CYCLE_END OUTPUT 9 GND 10 THSD_EN OUTPUT 11 GND 12 ERROR OUTPUT 13 GND 14 PROG<0> IN/OUT 15 GND 16 PROG<1> IN/OUT 17 GND 18 PROG<2> IN/OUT 19 GND 20 PROG<3> IN/OUT 21 GND 22 IDLE_SEL<0> IN/OUT 23 GND 24 IDLE_SEL<1> IN/OUT 25 GND 26 REMOTE_ENABLE INPUT 27 GND 28 REMOTE_START INPUT 29 GND 30 REMOTE_STOP INPUT 31 GND 32 REMOTE_RESET INPUT Table 29. FPGA PMOD connectors (J8) not mounted on the board Pin number Description Pin number Description 1 Not used 2 Not used 3 Not used 4 Not used 5 GND 6 3.3 V 7 Not used 8 Not used 9 Not used 10 Not used 11 GND 12 3.3 V |
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