Cycling endurance

AN4653

6/13

DocID027438 Rev 1

Figure 1. Safe cycling operating conditions (per byte) vs. temperature(1)

1. For temperatures lower than 25°C, the safe operating conditions are considered as 4 million cycles (the

real limit is actually higher)

For a robust application design, the safe cycling operating area shown in Figure 1 has to be

considered as a maximum cycling value for each byte of the memory, going above this safe

operating area is not recommended.

Note:

The cycling limits measured on the CMOS F8H process devices are much more above the

safe conditions offered on Figure 1.

1.2.2

Cycling qualification method

performance over the full temperature range. During the qualification phase, the parts are

cycled and then read in order to locate eventual failing bit.

In STMicroelectronics, the CMOS F8H process EEPROM intrinsic failure criterion is defined

as 1 failing cell (or less) over 10 million cells.

1.2.3

Overall number of write cycles

When evaluating the cycling performances of an application, it must be stressed out that the

number of cycles can be defined either for each memory cell or for the overall number of

cycles decoded by the whole memory:

–

the max cycling value defined in the datasheet is the max number of cycles for

each byte;

–

the overall number of cycles is the number of cycles correctly decoded and

executed by the device, spread over all addressed locations in the memory.

The characterization trials performed on high density CMOS F8H process products have

demonstrated that the overall number of write cycles can reach 1 Billion without failure, at

25°C (test performed on M95M01, 1Mbit device).

a. intrinsic = belonging to the essential nature or constitution of the EEPROM die (extrinsic = originating from

random event)