Cycling endurance

AN4653

8/13

DocID027438 Rev 1

In addition, to optimize the number of cycles in the EEPROM and keep the other data blocks

safe in the memory array:

•

define data classes (located in the same page) where data with similar update rates are

gathered together. This will optimize the use of the Page mode instead of the byte

mode;

•

the areas containing the read-only parameters and the cycled items should be

separated and made as much as possible independent from each other. Two types of

data should not share the same pages and, where possible, the same locations inside

the related page.

1.3.2

Cycling with Error Correction Code (ECC)

The CMOS F8H process high density devices offer an Error Correction Code (ECC) logic.

The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a

single bit out of the four bytes happens to be erroneous during a Read operation, the ECC

detects this bit and replaces it with the correct value. The read reliability is therefore much

improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be

written/cycled independently. In this case, the ECC function also writes/cycles the three

other bytes located in the same group. As a consequence, the maximum cycling budget is

defined at group level and the cycling can be distributed over the four bytes of the group: the

sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain

below the maximum value defined in Table 3: Application cycling profile evaluation.