DocID027483 Rev 1

11/21

AN4655

SW methods

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If the bit-banged interface is not to have a detrimental effect on real-time performance, then

it must be performed with a low priority and then it can’t be deterministic in terms of data

throughput and latency.

A specific problem could happen due to code alignment when the same code placed and

executed from different starting addresses. This can produce different timing of provided

signals. It is caused by different pipe line mechanism when code is fetched from the memory

in advance or flushed out from pipeline. User has to respect setting of instruction prefetch

and instruction and data cashing.

The most CPU efficient transfer is achieved by using a hardware interface and DMA transfer

to minimize the software overhead and cpu load. Bit-banging is at the opposite extreme of

that. It is neither portable nor flexible enough to handle all peripherals’ instances. The

produced signals normally have more jitter or glitches, especially if the controller is also

executing other tasks. That is why such communicating should be avoided in real time

critical environment especially.

Using specific macros and conditional code can increase code visibility significantly and

bring a sure level of flexibility even at this low level of programing (see the code examples).

Combination of bit-banging and interrupts can give a good fairly autonomous and interrupt

driven bit-banging code, only at the expense of using a dedicated timer. But in general, it is

very hard to do reliable bit-banging at high speeds in a multitasking environment.

2.4

Peripherals specific aspects of SW emulation

2.4.1

SPI

SW emulation of SPI is the simplest and easily adaptable as it is synchronous and no

specific requirements limit the rates, timing of signals or physical interface characteristic.

Data transmission and reception is provided contemporary on two separated data

unidirectional lines (MOSI, MISO) synchronized by common clock signal line provided by

master. No addressing or acknowledgment control is implemented.

Concerning SCK clock signal, the user has to respect fixed clock phase and polarity

between communicating nodes, even if different settings can be used for a group of nodes

within a single net if their communication is held separated. For slave select signal, negative

polarity is commonly expected. SS signal is often not implemented when simple

communication is done between a single pair of nodes with fixed master and slave roles.

Multi-master environment can be supported as well but there is no specific arbitration

except SS signal level. SPI node can provide a transaction when its SS input stays inactive

else multi-master conflict is recognized. In spite of full duplex communication is considered

as standard case, many solutions use simplified simplex communication (SPI node can be

transmitter or receiver only).

Clock signal can be continuous or not, no clock signal stretching is supported. This puts

limits especially on slave, because any transaction can start or continue regardless if any

data is ready or accepted on slave side. As a consequence, slave can easily enter in data

underrun or data overrun conditions.

The number of bits to be transacted is fixed between nodes but arbitrarily configurable.

Optional API can integrate single data buffering or more complex FIFO structures for both

transmitter and receiver.