SW methods

AN4655

16/21

DocID027483 Rev 1

#define setup_dly() {};/* no code is provided */

#define half_bit_dly() {};

2.5.3

I2C master bit-banging sequence

This example is related to procedures controlling I2C master 8 bits data frame read and

write transactions.

#define i2c_bus_init() { I2C_DR |= ((1 << I2C_SDA_PIN) | (1 <<

I2C_SCL_PIN)); }

#define i2c_set_sda() { I2C_DR |= (1 << I2C_SDA_PIN); }

#define i2c_clear_sda() { I2C_DR &= ~(1 << I2C_SDA_PIN); }

#define i2c_get_sda()

(I2C_DR & I2C_SDA_PIN)

#define i2c_set_scl() { I2C_DR |= (1 << I2C_SCL_PIN); }

#define i2c_clear_scl() { I2C_DR &= ~(1 << I2C_SCL_PIN); }

#define sda_wr_control(b) { (b & msk) ?

i2c_set_sda() : i2c_clear_sda(); }

#define sda_rd_control(b) { I f(i2c_get_sda() != 0)

b |= msk;

}

/**

* @brief I2C master write 8-bit data bit-bang

* @param unsigned char b - data to transmit

* @retval unsigned char ack – acknowledgement received

*/

void I2C_master_write (unsigned char b)

{

unsigned char msk = 0x80;

unsigned char ack;

do

{

sda_wr_control(b);

setup_dly();

i2c_set_scl();

half_bit_dly();

i2c_clear_scl();

setup_dly();

}

while ((msk>>=1) != 0);

i2c_set_sda();/* ACK slot checking */

i2c_set_scl();

half_bit_dly();

ack = i2c_get_sda();

i2c_clear_scl();

return (ack);

}