UPD750004A datasheet(10/84 Pages) NEC

10 / 84 page

µPD750004, 750006, 750008, 750004(A), 750006(A), 750008(A)

3.2

NON-PORT PINS

Notes 1. The circle (

) indicates the Schmitt trigger input.

2. With a noise eliminator/asynchronously selectable

3. Asynchronous

Function

Inputs external event pulse to the timer/event

counter

Timer/event counter output

Timer counter output

Clock output

Arbitrary frequency output (for buzzer output or

system clock trimming)

Serial clock I/O

Serial data output

Serial data bus I/O

Serial data input

Serial data bus I/O

Edge detection vectored interrupt input (both

rising and falling edges are detected)

Rising edge detection testable input

Falling edge detection testable input

Crystal/ceramic connection pin for main system

clock generation. When external clock signal is

used, it is applied to X1, and its reverse phase

signal is applied to X2.

Crystal connection pin for subsystem clock

generation. When external clock signal is used, it

is applied to XT1, and it reverse phase signal is

applied to XT2.

XT1 can be used as a 1-bit input (test).

System reset input (active low)

Internally connected. (To be connected directly to

VDD)

Positive power supply

Ground potential

Input/

output

Input

Output

I/O

Input

I/O

Input

When reset

Input

Edge detection vectored interrupt input

(detection edge selectable). A noise eliminator

can be selected when INT0/P10 is used.

Shared

P13

P20

P21

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60 - P63

P70 - P73

Note 3

Note 2

Note 3

I/O circuit

typeNote 1

-C

E-B

-A

-B

-C

-A

Pin name

TI0

PTO0

PTO1

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0 - KR3

KR4 - KR7

XT1

XT2

RESET

VDD

VSS

UPD750004A Datasheet(PDF) 10 Page - NEC

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