UPD750064CU datasheet(31/82 Pages) NEC

31 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

Figure 6-7. Timer/Event Counter Block Diagram (Channel 1)

PORT1.2

Input

buffer

TI1/P12/INT2

Timer/event counter output

(channel 0)

From clock

generator

MPX

–

TM16 TM15 TM14 TM13 TM12 TM11 TM10

TM1

Decoder

16 bit timer/event

counter mode

Timer operation start

Clear

Modulo register (8)

Comparator (8)

Count register (8)

Timer/event counter (channel 0) match signal/operation start

(When 16-bit timer/event counter mode)

Timer/event counter (channel 0) comparator

(When 16-bit timer/event counter mode)

TMOD1

Match

TOUT

F/F

Reset

enable flag

P21

output latch

Port 2

input/output

mode

INTT1

IRQT1

set signal

IRQT1

clear signal

RESET

TOE1

PORT2.1

PMGB bit 2

P21/PTO1

Output

buffer

Internal bus

Timer/event counter (channel 0) TM02 signal

(When 16-bit timer/event counter mode)

Selector

fX/22

fX/26

fX/28

fX/210

fX/212

UPD750064CU Datasheet(PDF) 31 Page - NEC

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