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UPD750064CU Datasheet(PDF) 60 Page - NEC |
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UPD750064CU Datasheet(HTML) 60 Page - NEC |
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60 / 82 page ![]() µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) 60 Data Sheet U10165EJ2V0DS00 DC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply currentNote 1 IDD1 VDD = 5.0 V ±10%Note 3 2.2 6.6 mA VDD = 3.0 V ±10%Note 4 0.48 1.5 mA IDD2 HALT VDD = 5.0 V ±10% 0.86 2.6 mA mode VDD = 3.0 V ±10% 0.43 1.3 mA IDD1 VDD = 5.0 V ±10%Note 3 1.7 4.5 mA VDD = 3.0 V ±10%Note 4 0.4 1.2 mA IDD2 HALT VDD = 5.0 V ±10% 0.7 2 mA mode VDD = 3.0 V ±10% 0.39 1.2 mA IDD3 Low- VDD = 3.0 V ±10% 11 33 µA voltage VDD = 2.0 V ±10% 5.5 17 µA modeNote 6 VDD = 3.0 V, TA = 25˚C 11 22 µA VDD = 3.0 V ±10% 9.2 27 µA VDD = 3.0 V, TA = 25˚C 9.2 18 µA IDD4 HALT Low- VDD = 3.0 V ±10% 6.4 20 µA mode voltage VDD = 2.0 V ±10% 2.5 8 µA modeNote 6 VDD = 3.0 V, TA = 25˚C 6.4 12.8 µA VDD = 3.0 V ±10% 4.6 13.8 µA VDD = 3.0 V, TA = 25˚C 4.6 9.2 µA IDD5 XT1 = VDD = 5.0 V ±10% 0.05 10 µA 0 VNote 8 VDD = 3.0 V ±10% 0.02 5 µA STOP mode TA = 25˚C 0.02 3 µA Notes 1. The current flowing to the internal pull-up resistor is not included. 2. Including the case when the subsystem clock oscillates. 3. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 4. When the device operates in low-speed mode with PCC set to 0000. 5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 6. When the sub-oscillation circuit control register (SOS) is set to 0000. 7. When SOS is set to 0010. 8. When SOS is set to 00 ×1, and the sub-oscillation circuit feedback resistor is not used (×: don’t care). 6.0-MHzNote 2 crystal oscillation C1 = C2 = 22 pF 4.19-MHz Note 2 crystal oscillation C1 = C2 = 22 pF 32.768- kHzNote 5 crystal oscillation Low current dissipation modeNote 7 Low current dissipation modeNote 7 |
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