LTC1645CS datasheet(8/24 Pages) LINER

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LTC1645

Power Supply Ramping

The power supplies on a board are controlled by placing

external N-channel pass transistors in the power paths as

shown in Figure 2. Consult Table 1 for a selection of

N-channel FETs suitable for use with the LTC1645. RSENSE1

and RSENSE2 provide current fault detection and R1 and R2

prevent high frequency oscillation. By ramping the gates

of the pass transistors up and down at a controlled rate,

the transient surge current (I = C • dv/dt) drawn from the

main backplane supply is limited to a safe value when the

board makes connection.

When power is first applied to the chip, the gates of the

N-channels (GATE1 and GATE2 pins) are pulled low. After

the ON pin is held above 0.8V for at least one timing cycle,

the voltage at GATE1 begins to rise with a slope equal to

dv/dt = 10

µA/C1 (Figure 3), where C1 is the external

capacitor connected between the GATE1 pin and GND. If

the ON pin is brought above 2V (and the ON pin has been

held above 0.8V for at least one timing cycle), the voltage

at GATE2 begins to rise with a slope equal to dv/dt =

µA/C2.

The ramp time for each supply is t = (VCCn • Cn)/10µA. If

the ON pin is pulled below 2V for GATE2 or 0.8V for GATE1

(but above 0.4V), a 40

µAcurrentsourceisconnectedfrom

GATE

n to GND, and the voltage at the GATEn pin will ramp

down, as shown in Figure 4.

Ringing

Good engineering practice calls for bypassing the supply

rail of any circuit. Bypass capacitors are often placed at the

supply connection of every active device, in addition to one

or more large value bulk bypass capacitors per supply rail.

If power is connected abruptly, the bypass capacitors slow

the rate of rise of voltage and heavily damp any parasitic

resonance of lead or trace inductance working against the

supply bypass capacitors.

The opposite is true for LTC1645 Hot Swap circuits on a

daughterboard. In most cases, on the powered side of the

N-channel FET switches (VCCn) there is no supply bypass

capacitor present. An abrupt connection, produced by

plugging a board into a backplane connector, results in a

fast rising edge applied to the VCCn line of the LTC1645.

APPLICATIO S I FOR ATIO

Figure 4. Supply Turning Off

Figure 3. Supply Turning On

Figure 2. Typical Hot Swap Connection

RSENSE2

Ω

CTIMER

CLOAD1

CLOAD2

Ω

VCC1

FAULT

SENSE1

GATE2

VCC2

VCC1

VOUT2

VOUT1

LTC1645

(14-LEAD)

TIMER

GND

COMP+

COMPOUT

SENSE2

GATE1

1645 F02

RESET

RSENSE1

VCCn

VOUTn

VCCn + ∆VGATE

1645 F03

GATE

SLOPE = 10

µA/Cn

VCCn

VOUTn

VCCn + ∆VGATE

1645 F04

GATE

SLOPE = 40

µA/Cn

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