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LTC1645CS Datasheet(PDF) 21 Page - Linear Technology |
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LTC1645CS Datasheet(HTML) 21 Page - Linear Technology |
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21 / 24 page  21 LTC1645 Table 1. N-Channel Selection Guide CURRENT PART LEVEL NUMBER MANUFACTURER DESCRIPTION 1A to 2A NDH8503N Fairchild Dual N-Channel RDS(ON) = 0.033 SuperSOT-8 1A to 2A Si6928DQ Siliconix Dual N-Channel RDS(ON) = 0.035 TSSOP-8 2A to 5A Si4920DY Siliconix Dual N-Channel RDS(ON) = 0.025 SO-8 2A to 5A IRF7313 International Dual N-Channel Rectifier RDS(ON) = 0.029 SuperSOT-8 5A to 10A Si4420 Siliconix Single N-Channel RDS(ON) = 0.009 SO-8 5A to 10A FDS6680 Fairchild Single N-Channel RDS(ON) = 0.01 SO-8 5A to 10A IRF7413 International Single N-Channel Rectifier RDS(ON) = 0.011 SO-8 5A to 10A MMSF3300 ON Semiconductor Single N-Channel RDS(ON) = 0.0125 SO-8 10A to 20A FDB8030L Fairchild Single N-Channel RDS(ON) = 0.0035 TO-263AB 10A to 20A SUD75N03-04 Siliconix Single N-Channel RDS(ON) = 0.004 D2PAK ON 2V/DIV VOUT2 2V/DIV VREGOUT 2V/DIV Figure 24. Switching Regulator Hot Swap VOUT1 2V/DIV VREGIN 2V/DIV RESET 5V/DIV APPLICATIO S I FOR ATIO VCC VOUT *USER SELECTED VOLTAGE CLAMP 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET 1645 F25 R1 D1* D2 1N4148 D4* D2 1N4148 Q1 Figure 25. Optional Gate Clamp its FB or SENSE pin. In the case of the LTC1649, large peak currents result if the FB pin is at ground and not connected directly to the output inductor and capacitors. To keep the peak currents under control, R1, R2 and D1 hold the FB pin above ground but below its normal regulated value until VOUT2 ramps up and D1 reverse-biases. Power N-Channel Selection The RDS(ON) of the external pass transistors must be low enough so that the voltage drop across them is 100mV or less at full current. If the RDS(ON) is too high, the voltage drop across the transistor can cause the output voltage to trip the reset circuit. The transistors listed in Table 1 or other similar transistors are recommended for use with the LTC1645. Low voltage applications may require the use of logic-level FETs; ensure their maximum VGS rating is sufficient for the application. GATE voltage as a function of VCC is illustrated in the Typical Performance curves. If lower GATE drive is desired, connect a diode in series with a zener between GATE and VCC or between GATE and VOUT as shown in Figure 25. |
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