LTC1645CS datasheet(9/24 Pages) LINER

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LTC1645

APPLICATIO S I FOR ATIO

(a) Undamped VCC Waveform (48" Leads)

(b) Undamped VCC Waveform (8" Leads)

Figure 5. Ring Experiment

No bulk capacitance is present to slow the rate of rise and

heavily damp the parasitic resonance. Instead, the fast

edge shock excites a resonant circuit formed by a combi-

nation of wiring harness, backplane and circuit board

parasitic inductances and FET capacitance. In theory, the

peak voltage should rise to 2X the input supply, but in

practice the peak can reach 2.5X, owing to the effects of

voltage dependent FET capacitance.

The absolute maximum VCCn potential for the LTC1645 is

13.2V; any circuit with an input of 5V or greater should be

scrutinized for ringing. A well-bypassed backplane should

not escape suspicion: circuit board trace inductances of as

little as 10nH can produce sufficient ringing to overvoltage

VCC.

Check ringing with a fast storage oscilloscope (such as a

LECROY 9314AL DSO) by attaching coax or a probe to VCC

and GND, then repeatedly inserting the circuit board into

the backplane. Figures 5a and 5b show typical results in a

12V application with different VCC lead lengths. The peak

amplitude reaches 22V, breaking down the ESD protection

diode in the process.

There are two methods for eliminating ringing: clipping

and snubbing. A transient voltage suppressor is an effec-

tive means of limiting peak voltage to a safe level.

Figure 6 shows the effect of adding an ON Semiconductor,

1SMA12CAT3, on the waveform of Figure 5.

Figures 7a and 7b show the effects of snubbing with

different RC networks. The capacitor value is chosen as

10X to 100X the FET COSS under bias and R is selected for

best damping—1

Ω to 50Ω depending on the value of

parasitic inductance.

VOUT

0.1

µF

1645 F05

Ω

0.01

Ω

12V

IRF7413

CLOAD

–

LTC1645

POWER

LEADS

SCOPE

PROBE

µs/DIV

1645 F05a

24V

µs/DIV

1645 F05b

24V

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