LTC1645CS datasheet(5/24 Pages) LINER

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LTC1645

VCC2 (Pin 1/Pin 1): Positive Supply Input. VCC2 can range

from 1.2V to 12V for normal operation. ICC2 is typically

0.2mA. An undervoltage lockout circuit disables the

LTC1645 whenever the voltage at VCC2 is less than 1.12V.

SENSE2 (Pin 2/Pin 2): VCC2 Circuit Breaker Set Pin. With

a sense resistor placed in the supply path between VCC2

and SENSE2, the circuit breaker trips when the voltage

across the resistor exceeds 50mV for more than 1.5

µs. If

the circuit breaker trip current is set to twice the normal

operating current, only 25mV is dropped across the sense

resistor during normal operation. To disable the circuit

breaker, short VCC2 and SENSE2 together.

GATE2 (Pin 3/Pin 3): Channel 2 High Side Gate Drive.

Connect to the gate of an external N-channel MOSFET. An

internal charge pump guarantees at least 4.5V of gate

drive. The charge pump is powered by the higher of VCC1

and VCC2. When the ON pin exceeds 2V, GATE2 is turned

on by connecting a 10

µA current source from the charge

pump output to the GATE2 pin and the voltage starts to

ramp up with a slope dv/dt = 10

µA/CGATE2. While the ON

pin is below 2V but above 0.4V, a 40

µA current source

pulls GATE2 toward ground. If the ON pin is below 0.4V,

the circuit breaker trips or the undervoltage lockout circuit

trips, the GATE2 pin is immediately pulled to ground with

a 12mA (typ) current source.

FAULT (Pin 4/NA): Circuit Breaker Fault. FAULT is an

open-drain output that pulls low when the circuit breaker

function trips. The circuit breaker is reset by pulling the ON

pin below 0.4V. An external pull-up is required to generate

a logic high at the FAULT pin. When the ON pin is low,

FAULT will release.

The circuit breaker can be programmed to automatically

reset by connecting the FAULT pin to the ON pin. In this

circuit configuration, if a logic device is driving the ON pin,

use a series resistor between the logic output and the ON

pin to prevent large currents from flowing.

RESET (Pin 5/NA): Open-Drain RESET Output. The RESET

pin is pulled low when the voltage at the FB pin goes below

1.238V or VCC1 is below the undervoltage lockout thresh-

old. The RESET pin goes high one timing cycle after the

voltage at the FB pin goes above the FB pin threshold. The

ON pin must remain above 0.8V during this timing cycle.

An external pull-up is required to generate a logic high at

the RESET pin.

FB (Pin 6/NA): RESET Comparator Input. The FB pin is

used to monitor the output supply voltage with an external

resistive divider. When the voltage on the FB pin is lower

than 1.238V, the RESET pin is pulled low. A glitch filter on

the FB pin prevents fast transients from forcing RESET

low. When the voltage on the FB pin rises above the trip

point, the RESET pin goes high after one timing cycle.

GND (Pin 7/Pin 4): Ground. Connect to a ground plane for

optimum performance.

COMP+ (Pin 8/NA): Spare Comparator Noninverting In-

put. When the voltage on COMP+ is lower than 1.238V,

COMPOUT pulls low.

COMPOUT (Pin 9/NA): Open-Drain Spare Comparator

Output. COMPOUT pulls low when the voltage on COMP+

is below 1.238V or VCC1 is below the undervoltage lockout

threshold. An external pull-up is required to generate a

logic high at the COMPOUT pin.

ON (Pin 10/Pin 5): Analog Control Input. If the ON pin

voltage is below 0.4V, both GATE1 and GATE2 are imme-

diately pulled to ground. While the voltage is between 0.4V

and 0.8V, both GATE1 and GATE2 are each pulled to

ground with a 40

µA current source. While the voltage is

between 0.8V and 2V, the GATE1 pull-up is turned on after

one timing cycle, but GATE2 continues to be pulled to

ground with a 40

µA current source. When the voltage

exceeds 2V, both the GATE1 and GATE2 pull-ups are

turned on one timing cycle after the voltage exceeds 0.8V.

The ON pin is also used to reset the electronic circuit

breaker. If the ON pin is brought below and then above

0.4V following the trip of the circuit breaker, the circuit

breaker resets, and a normal power-up sequence occurs.

TIMER: (Pin 11/NA): System Timing Pin. The TIMER pin

requires an external capacitor to ground to generate a

timing delay. The pin is used to set the delay before the

RESET pin goes high after the output supply voltage is

good as sensed by the FB pin. It is also used to set the delay

between the ON pin exceeding 0.8V and the GATE1 and

GATE2 pins turning on (GATE2 turns on only if the ON pin

exceeds 2V).

(14-Lead Package/8-Lead Package)

PI FU CTIO S

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