MAX127ACAI datasheet(6/16 Pages) MAXIM

6 / 16 page

Multirange, +5V, 12-Bit DAS with

2-Wire Serial Interface

_______________________________________________________________________________________

TIMING CHARACTERISTICS (continued)

(VDD = +4.75V to +5.25V; unipolar/bipolar range; external reference mode, VREF = 4.096V; 4.7µF at REF pin; TA = TMIN to TMAX;

unless otherwise noted. Typical values are at TA = +25°C.)

Note 1:

Accuracy specifications tested at VDD = 5.0V. Performance at power-supply tolerance limits is guaranteed by Power-

Supply Rejection test.

Note 2:

External reference: VREF = 4.096V, offset error nulled, ideal last-code transition = FS - 3/2LSB.

Note 3:

Ground “on” channel, sine wave applied to all “off” channels.

Note 4:

Guaranteed by design. Not tested.

Note 5:

Use static external load during conversion for specified accuracy.

Note 6:

Tested using internal reference.

Note 7:

PSRR measured at full scale. Tested for the ±10V (MAX127) and ±4.096V (MAX128) input ranges.

Note 8:

Not subject to production testing. Provided for design guidance only.

PARAMETERS

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

Low Period of the SCL Clock

tLOW

4.7

µs

High Period of the SCL Clock

tHIGH

4.0

µs

Setup Time for a Repeated

START Condition

tSU, STA

4.7

µs

Data Hold Time

tHD, DAT

0.9

µs

Data Setup Time

tSU, DAT

250

Rise Time for Both SDA and SCL

Signals (Receiving)

1000

Fall Time for Both SDA and SCL

Signals (Receiving)

300

Fall Time for Both SDA and SCL

Signals (Transmitting)

Cb = total capacitance of one bus line in pF,

up to 6mA sink

20 +

250

0.1 x Cb

Setup Time for STOP Condition

tSU, STO

4.0

µs

Capacitive Load for Each

Bus Line

400

Pulse Width of Spike Suppressed

tSP

Hold Time (Repeated) START

Condition

tHD,STA

4.0

µs

Bus Free Time Between a STOP

and START Condition

tBUF

4.7

µs

SCL Clock Frequency

fSCL

100

kHz

2-WIRE STANDARD MODE

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