ICS84330CVI REVISION A JANUARY 7, 2011

4

©2011 Integrated Device Technology, Inc.

ICS84330CI Data Sheet

720MHZ, CRYSTAL-TO-LVPECL FREQUENCY SYNTHESIZER

Function Tables

Table 3A. Parallel and Serial Mode Function Table

NOTE:

L = LOW

H = HIGH

X = Don’t care

 = Rising edge transition

 = Falling edge transition

Table 3B. Programmable VCO Frequency Function Table

NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.

Table 3C. Programmable Output DividerFunction Table

Inputs

Conditions

nP_LOAD

M

N

S_LOAD

S_CLOCK

S_DATA

X

X

X

X

X

X

Reset. M and N bits are all set HIGH.

L

Data

Data

X

X

X

Data on M and N inputs passed directly to the M divider and

N output divider. TEST mode 000.



Data

Data

L

X

X

Data is latched into input registers and remains loaded until next

LOW transition or until a serial event occurs.

HX

X

L



Data

Serial input mode. Shift register is loaded with data on S_DATA on

each rising edge of S_CLOCK.

HX

X



LData

Contents of the shift register are passed to the M divider and

N output divider.

HX

X



L

Data

M divider and N output divider values are latched.

H

X

X

L

X

X

Parallel or serial input do not affect shift registers.

HX

X

H



Data

S_DATA passed directly to M divider as it is clocked.

VCO Frequency

(MHz)

M Divide

256

128

64

32

16

8

4

2

1

M8

M7

M6

M5

M4

M3

M2

M1

M0

250

125

0

0

1111

10

1

252

126

0

0

1111

11

0

254

127

0

0

1111

10

1

256

128

0

1

0000

01

0

•

•

•

••••

•

•

•

•

•

•

•

••••

•

•

•

•

718

359

1

0

1100

11

1

720

360

1

0

1101

00

0

Inputs

N Divider Value

Output Frequency (MHz)

N1

N0

Minimum

Maximum

00

2

125

360

01

4

62.5

180

1

0

8

31.25

90

11

1

250

720