Digitally Controlled Analog I/O Processor

8

MX839 PRELIMINARY INFORMATION

© 1998 MX

xCOM Inc.

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Doc. # 20480164.002

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4.5.2

Write Only Register (8-Bit and 16-Bit)

HEX

ADDRESS/

COMMAN

D

REGISTER

NAME

BIT 7

(D7)

BIT 6

(D6)

BIT 5

(D5)

BIT 4

(D4)

BIT 3

(D3)

BIT 2

(D2)

BIT 1

(D1)

BIT 0

(D0)

$01

RESET

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

CLOCK

DIVIDER

$D0

CONTROL

0

0

0

0

0

BIT 2

BIT 1

BIT 0

VARIABLE

MOD1

MOD1

$D2

ATTENUATOR (1)

0

0

ENABLE

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

VARIABLE

MOD2

MOD2

ATTENUATOR (2)

0

0

ENABLE

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DAC

NBIT

NBIT

NBIT

DAC1

DAC2

DAC3

$D3

CONTROL

DAC1

DAC2

DAC3

0

ENABLE

ENABLE

ENABLE

0

DAC1 DATA

$D4

(1)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

*See Note 1

(2)

0

0

0

0

0

0

BIT 9

BIT 8

DAC2 DATA

$D5

(1)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

*See Note 1

(2)

0

0

0

0

0

0

BIT 9

BIT 8

DAC3 DATA

$D6

(1)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

*See Note 1

(2)

0

0

0

0

0

0

BIT 9

BIT 8

A/D

A/DIN1

A/DIN2

A/DIN3

A/DIN4

$D7

CONTROL

0

1

READ

ACTIVE

ACTIVE

ACTIVE

ACTIVE

0

MAG COMP ONE

MAGNITUDE COMPARATOR UPPER LEVEL

$D8

LEVELS (1)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MAG COMP ONE

MAGNITUDE COMPARATOR LOWER LEVEL

LEVELS (2)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MAG COMP TWO

MAGNITUDE COMPARATOR UPPER LEVEL

$D9

LEVELS (1)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MAG COMP TWO

MAGNITUDE COMPARATOR LOWER LEVEL

LEVELS (2)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MAG COMP THREE

MAGNITUDE COMPARATOR UPPER LEVEL

$DA

LEVELS (1)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MAG COMP THREE

MAGNITUDE COMPARATOR LOWER LEVEL

LEVELS (2)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MAG COMP FOUR

MAGNITUDE COMPARATOR UPPER LEVEL

$DB

LEVELS (1)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MAG COMP FOUR

MAGNITUDE COMPARATOR LOWER LEVEL

LEVELS (2)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Table 2: Write Only Register (8-Bit and 16-Bit)

Note

1.

A second byte is expected by the 'C-BUS' interface only when the 'NBIT DAC

n' bit of the 'DAC Control Register' is

set high. Otherwise, the data transfer is a single byte (Bit 7 to Bit 0).