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DB929B Datasheet(PDF) 3 Page - CML Microcircuits

Part # DB929B
Description  Full Data Packet Framing
PDF  51 Pages
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Manufacturer  CMLMICRO [CML Microcircuits]
Direct Link  http://www.cmlmicro.com
Logo CMLMICRO - CML Microcircuits

DB929B Datasheet(HTML) 3 Page - CML Microcircuits

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4-Level FSK Modem Data Pump
Page 3 of 50
MX929B PRELIMINARY INFORMATION
©2001 MX-COM, INC.
www.mxcom.com Tel: 800 638 5577 336 744 5050
Fax: 336 744 5054
Doc. # 20480171.003
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
All trademarks and service marks are held by their respective companies.
4.5.2.16
TIB: Transmit Intermediate Block ............................................................................... 21
4.5.2.17
TLB: Transmit Last Block ........................................................................................... 21
4.5.2.18
T4S: Transmit 4 Symbols ........................................................................................... 21
4.5.2.19
TSID: Transmit Station ID ............................................................................................ 22
4.5.2.20
RESET: Stop any current action................................................................................. 22
4.5.2.21
Task Timing................................................................................................................ 22
4.5.2.22
RRC Filter Delay......................................................................................................... 23
4.5.3
Control Register .................................................................................................................... 24
4.5.3.1
Control Register B7, B6: CKDIV - Clock Division Ratio.............................................. 24
4.5.3.2
Control Register B5, B4: FSTOL - Frame Sync Tolerance to Inexact Matches ......... 24
4.5.3.3
Control Register B3, B2: LEVRES - Level Measurement Modes ............................... 25
4.5.3.4
Control Register B1, B0: PLLBW - Phase-Locked Loop Bandwidth Modes............... 25
4.5.4
Mode Register....................................................................................................................... 26
4.5.4.1
Mode Register B7: IRQEN - IRQ Output Enable....................................................... 26
4.5.4.2
Mode Register B6: INVSYM - Invert Symbols ............................................................ 26
4.5.4.3
Mode Register B5:
RX
TX/
- Tx/Rx Mode.................................................................. 26
4.5.4.4
Mode Register B4: RXEYE - Show Rx Eye ................................................................ 27
4.5.4.5
Mode Register B3: PSAVE - Powersave.................................................................... 27
4.5.4.6
Mode Register B2: SSIEN - 'S' Symbol IRQ Enable .................................................. 27
4.5.4.7
Mode Register B1, B0: SSYM - 'S' Symbol To Be Transmitted................................. 27
4.5.5
Status Register ..................................................................................................................... 28
4.5.5.1
Status Register B7: IRQ - Interrupt Request .............................................................. 28
4.5.5.2
Status Register B6: BFREE - Data Block Buffer Free................................................ 28
4.5.5.3
Status Register B5: IBEMPTY - Interleave Buffer Empty........................................... 28
4.5.5.4
Status Register B4: DIBOVF - De-Interleave Buffer Overflow ................................... 29
4.5.5.5
Status Register B3: CRCERR - CRC Checksum Error.............................................. 29
4.5.5.6
Status Register B2: 'S' Symbol Ready........................................................................ 29
4.5.5.7
Status Register B1, B0: SVAL - Received 'S' Symbol Value...................................... 29
4.5.6
Data Quality Register ............................................................................................................ 29
4.6 CRC, FEC and Interleaving.............................................................................................. 30
4.6.1
Cyclic Redundancy Codes .................................................................................................... 30
4.6.1.1
CRC0.......................................................................................................................... 30
4.6.1.2
CRC1.......................................................................................................................... 30
4.6.1.3
CRC2.......................................................................................................................... 30
4.6.1.4
Forward Error Correction............................................................................................ 30
4.6.1.5
Interleaving ................................................................................................................. 31
4.7 Transmitted Symbol Shape.............................................................................................. 31



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