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PIC17C752 Datasheet(PDF) 124 Page - Microchip Technology |
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PIC17C752 Datasheet(HTML) 124 Page - Microchip Technology |
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124 / 320 page ![]() PIC17C75X DS30264A-page 124 Preliminary © 1997 Microchip Technology Inc. FIGURE 15-4: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit7 bit0 bit 7: SMP: SPI data input sample phase SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode In I2C master or slave mode: 1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0= Slew rate control enabled for high speed mode (400 kHz) bit 6: CKE: SPI Clock Edge Select (Figure 15-8, Figure 15-11, and Figure 15-12) CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C slave mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only.This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only.This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. In I2C slave mode: 1 = Read 0 = Write In I2C master mode: 1 = Transmit is in progress 0 = Transmit is not in progress. Or’ing this bit with SAE, RCE, SPE, or AKE will indicate if the SSP is in IDLE mode. bit 1: UA: Update Address (10-bit I2C slave mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Data Transmit in progress (does not include ACK and stop bits), SSPBUF is full 0 = Data Transmit complete (does not include ACK and stop bits), SSPBUF is empty |
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