PIC17C752 datasheet(128/320 Pages) MICROCHIP

128 / 320 page

PIC17C75X

DS30264A-page 128

Preliminary

The block diagram of the SSP module, when in SPI

mode (Figure 15-7), shows that the SSPSR is not

directly readable or writable, and can only be accessed

by addressing the SSPBUF register. Additionally, the

SSP status register (SSPSTAT) indicates the various

status conditions.

FIGURE 15-7: SSP BLOCK DIAGRAM

(SPI MODE)

Read

Write

Internal

data bus

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

SS Control

Enable

Edge

Select

Clock Select

TMR2 output

TOSC

Prescaler

4, 16, 64

Edge

Select

Data to TX/RX in SSPSR

Data direction bit

SMP:CKE

SDI

SDO

SCK

To enable the serial port, SSP Enable bit, SSPEN

(SSPCON1<5>) must be set. To reset or reconﬁgure

SPI mode, clear bit SSPEN, re-initialize the SSPCON

registers, and then set bit SSPEN. This conﬁgures the

SDI, SDO, SCK, and SS pins as serial port pins. For the

pins to behave as the serial port function, some must

have their data direction bits (in the DDR register)

appropriately programmed. That is:

• SDI is automatically controlled by the SPI module

• SDO must have DDRB<7> cleared

• SCK (Master mode) must have DDRB<6> cleared

• SCK (Slave mode) must have DDRB<6> set

•SS must have PORTA<2> set

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (DDR) register to the opposite value. An example

would be in master mode where you are only sending

data (to a display driver), then both SDI and SS could

be used as general purpose open drain outputs by writ-

ing a ’0’.

Figure 15-9 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite

edge of the clock. Both processors should be pro-

grammed to same Clock Polarity (CKP), then both con-

trollers would send and receive data at the same time.

Whether the data is meaningful (or dummy data)

depends on the application software. This leads to

three scenarios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

Note: The SS pin must be conﬁgured as an input

for the slave select to operate. This is done

by writing a ’1’ to PORTA<2>.

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