RF65 datasheet(43/72 Pages) ETC2

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RF65

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ADVANCED COMMUNICATIONS & SENSING

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5.4. Continuous Mode

5.4.1. General Description

As illustrated in Figure 25, in Continuous mode the NRZ data from the demodulator is directly accessed by the uC on the

DIO2/DATA pin. The FIFO and packet handler are thus inactive.

CONTROL

DIO0

DIO1/DCLK

DIO2/DATA

DIO3

DIO4

DIO5

Data

SYNC

RECOG.

SPI

NSS

SCK

MOSI

MISO

Figure 25. Continuous Mode Conceptual View

5.4.2. Rx Processing

If the bit synchronizer is disabled, the raw demodulator output is made directly available on DATA pin and no DCLK signal

is provided.

Conversely, if the bit synchronizer is enabled, synchronous cleaned data and clock are made available respectively on

DIO2/DATA and DIO1/DCLK pins. DATA is sampled on the rising edge of DCLK and updated on the falling edge as

illustrated below.

DATA (NRZ)

DCLK

Figure 26. Rx Processing in Continuous Mode

Note

in Continuous mode it is always recommended to enable the bit synchronizer to clean the DATA signal even if the

DCLK signal is not used by the uC (bit synchronizer is automatically enabled in Packet mode).

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