PIC16LC712-04SLASHSS datasheet(55/108 Pages) MICROCHIP

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Preliminary

DS41106A-page 55

PIC16C712/716

9.4

Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (to a level of 1.5V - 2.1V). To take

advantage of the POR, just tie the MCLR pin directly (or

through a resistor) to VDD. This will eliminate external

RC components usually needed to create a Power-on

Reset. A maximum rise time for VDD is specified

(parameter D004). For a slow rise time, see Figure 9-5.

When the device starts normal operation (exits the

reset condition), device operating parameters (voltage,

frequency, temperature,...) must be met to ensure oper-

ation. If these conditions are not met, the device must

be held in reset until the operating conditions are met.

Brown-out Reset may be used to meet the start-up con-

ditions.

FIGURE 9-5:

EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

Note 1: External Power-on Reset circuit is required

only if VDD power-up slope is too slow. The

diode D helps discharge the capacitor

quickly when VDD powers down.

2: R < 40 k

Ω is recommended to make sure

that voltage drop across R does not violate

the device’s electrical specification.

3: R1 = 100

Ω to 1 kΩ will limit any current

flowing into MCLR from external capacitor

C in the event of MCLR/VPP pin break-

down due to Electrostatic Discharge

(ESD) or Electrical Overstress (EOS).

VDD

MCLR

PIC16C7XX

VDD

9.5

Power-up Timer (PWRT)

The Power-up Timer provides a fixed nominal time-out

(parameter #33), on power-up only, from the POR. The

Power-up Timer operates on an internal RC oscillator.

The chip is kept in reset as long as the PWRT is active.

The PWRT’s time delay allows VDD to rise to an accept-

able level. A configuration bit is provided to enable/dis-

able the PWRT.

The power-up time delay will vary from chip to chip due

to VDD, temperature, and process variation. See DC

parameters for details.

9.6

Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (from OSC1 input) delay after the

PWRT delay is over (parameter #32). This ensures that

the crystal oscillator or resonator has started and stabi-

lized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

9.7

Brown-Out Reset (BOD)

The PIC16C712/716 members have on-chip Brown-out

Reset circuitry. A configuration bit, BODEN, can disable

(if clear/programmed) or enable (if set) the Brown-out

Reset circuitry. If VDD falls below 4.0V, refer to VBOR

parameter D005(VBOR) for a time greater than param-

eter (TBOR) in Table 12-6. The brown-out situation will

reset the chip. A reset is not guaranteed to occur if VDD

falls below 4.0V for less than parameter (TBOR).

On any reset (Power-on, Brown-out, Watchdog, etc.)

the chip will remain in Reset until VDD rises above

VBOR. The Power-up Timer will now be invoked and will

keep the chip in reset an additional 72 ms.

If VDD drops below VBOR while the Power-up Timer is

running, the chip will go back into a Brown-out Reset

and the Power-up Timer will be re-initialized. Once VDD

rises above VBOR, the Power-Up Timer will execute a

72 ms reset. The Power-up Timer should always be

enabled when Brown-out Reset is enabled. Figure 9-7

shows typical Brown-out situations.

For operations where the desired brown-out voltage is

other than 4V, an external brown-out circuit must be

used. Figure 9-8, 9-9 and 9-10 show examples of exter-

nal brown-out protection circuits.

PIC16LC712-04/SS Datasheet(PDF) 55 Page - Microchip Technology

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