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PIC16LC712-04/SS Datasheet(PDF) 89 Page - Microchip Technology |
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PIC16LC712-04/SS Datasheet(HTML) 89 Page - Microchip Technology |
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89 / 108 page  PIC16C712/716 © 1999 Microchip Technology Inc. Preliminary DS41106A-page 89 FIGURE 12-8: A/D CONVERSION TIMING TABLE 12-8 A/D CONVERSION REQUIREMENTS Param No. Sym Characteristic Min Typ† Max Units Conditions 130 TAD A/D clock period Standard 1.6 —— µsTOSC based, VREF ≥ 3.0V Extended (LC) 2.0 — — µsTOSC based, VREF full range Standard 2.0 4.0 6.0 µs A/D RC Mode Extended (LC) 3.0 6.0 9.0 µs A/D RC Mode 131 TCNV Conversion time (not including S/H time) (Note 1) 11 — 11 TAD 132 TACQ Acquisition time Note 2 5* 20 — — — µs µs The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert → sample time 1.5 § — — TAD : * These parameters are characterized but not tested. : † Data in “Typ” column is at 5V, 25 °C unless otherwise stated. These parameters are for design guidance only and are not tested. : § This specification ensured by design. Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 9.1 for min conditions. 131 130 132 BSF ADCON0, GO Q4 A/D CLK A/D DATA ADRES ADIF GO SAMPLE OLD_DATA SAMPLING STOPPED DONE NEW_DATA (TOSC/2) (1) 7 6 5 432 1 0 Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 1 Tcy 134 |
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