PIC16C641-04ESLASHTQ datasheet(70/136 Pages) MICROCHIP

70 / 136 page

PIC16C64X & PIC16C66X

DS30559A-page 70

Preliminary

9.8

Power-Down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the STATUS register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin and the com-

parators and VREF module should be disabled. I/O pins

that are hi-impedance inputs should be pulled high or

low externally to avoid switching currents caused by

ﬂoating inputs. The T0CKI input should also be at VDD

or VSS for lowest current consumption. The contribu-

tion from on chip pull-ups on PORTB should be consid-

ered.

The MCLR pin must be at a logic high level (VIHMC).

9.8.1

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

Any device reset

Watchdog Timer Wake-up (if WDT was enabled)

Interrupt from RB0/INT pin, RB Port change, or

the Comparator.

The ﬁrst event will reset the device upon wake-up.

However the latter two events will wake the device and

then resume program execution. The TO and PD bits in

the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up is cleared when SLEEP is invoked. The TO

bit is cleared if WDT wake-up occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). Wake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have an NOP after the SLEEP instruction.

9.8.2

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and interrupt ﬂag set, one of the following events will

occur:

• If the interrupt occurs before the execution of a

SLEEP

instruction, the SLEEP instruction will com-

plete as an NOP. Therefore, the WDT and WDT

postscaler will not be cleared, the TO bit will not

be set and PD bit will not be cleared.

• If the interrupt occurs during or after the execution

of a SLEEP instruction, the device will immediately

wake-up from sleep. The SLEEP instruction will be

completely executed before the wake-up. There-

fore, the WDT and WDT postscaler will be

cleared, the TO bit will be set and the PD bit will

be cleared.

Even if the ﬂag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as an NOP.

To ensure that the WDT is clear, a CLRWDT instruction

should be executed before a SLEEP instruction.

FIGURE 9-19: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q3 Q4

Q1 Q2

Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q2 Q3

Q1 Q2

OSC1

CLKOUT(4)

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC+1

PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h

0005h

Dummy cycle

TOST(2)

PC+2

Note

1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

4: CLKOUT is not available in these osc modes, but shown here for timing reference.

PIC16C641-04E/TQ Datasheet(PDF) 70 Page - Microchip Technology

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