AP0202AT datasheet(9/54 Pages) ONSEMI

9 / 54 page

AP0202AT/D Rev. 4, Pub. 9/15 EN

©Semiconductor Components Industries, LLC, 2015.

AP0202AT: Image Signal Processor (ISP)

System Interfaces

Advance

2. ON Semiconductor recommends a 1.5kresistor value for the two-wire serial interface RPULL-UP;

however, greater values may be used for slower transmission speed.

3. RESET_BAR has an internal pull-up resistor and can be left floating if not used.

4. The decoupling capacitors for the regulator input and output should have a value of 1.0uF. The

capacitors should be ceramic and need to have X5R or X7R dielectric.

5. TEST and RESERVED_[1:0] connect to GND for normal operation.

6. ON Semiconductor recommends that 0.1F and 1F decoupling capacitors for each power supply

are mounted as close as possible to the pin. Actual values and numbers may vary depending on lay-

out and design consideration.

7. The diagram is showing Legacy mode. If Crossbar is used, the 27 parallel outputs can be assigned to

any pin. Refer to crossbar section for more details.

HiSPi and Parallel Connection

When using the HiSPi interface, connect the parallel interface to VDDIO_S.

When using the parallel interface, it is recommended for the HiSPi interface to be

connected to ground, and the power supply (VDD_PHY) to be connected to +2.8V.

Floating these pins is allowed as well.

Crystal Usage

As an alternative to using an external oscillator, a crystal may be connected between

EXTCLK and XTAL. Two small loading capacitors and a feedback resistor should be

added, as shown in Figure 4.

For applications above 85°C, ON Semiconductor does not recommend using the crystal

option. A crystal oscillator with temperature compensation is recommended for appli-

cations that require this.

Figure 4:

Using a Crystal Instead of an External Oscillator

Rf represents the feedback resistor, an Rf value of 1M is sufficient for AP0202AT. C1 and

C2 are decided according to the crystal or resonator CL specification. In the steady state

of oscillation, CL is defined as (C1 x C2)/(C1+C2). In fact, the I/O ports, the bond pad,

package pin and PCB traces all contribute the parasitic capacitance to C1 and C2. There-

fore, CL can be rewritten to be (C1* x C2*)/(C1*+C2*), where C1*=(C1+CIN, STRAY) and

EXTCLK

XTAL

AP0202AT

Rf=1M

AP0202AT Datasheet(PDF) 9 Page - ON Semiconductor