CS5307 datasheet(12/24 Pages) ONSEMI

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CS5307

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Enhanced V2 responds to disturbances in VCORE by

employing both “slow” and “fast” voltage regulation. The

internal error amplifier performs the slow regulation.

Depending on the gain and frequency compensation set by

the amplifier’s external components, the error amplifier will

typically begin to ramp its output to react to changes in the

output voltage in one or two PWM cycles. Fast voltage

feedback is implemented by a direct connection from Vcore

to the non−inverting pin of the PWM comparator via the

summation with the inductor current, internal ramp and

offset. A rapid increase in output current will produce a

negative offset at Vcore and at the output of the summer.

This will cause the PWM duty cycle to increase almost

instantly. Fast feedback will typically adjust the PWM duty

cycle in one PWM cycle.

As shown in Figure 14, an internal ramp (nominally 115 mV

at a 50% duty cycle) is added to the inductor current ramp

at the positive terminal of the PWM comparator. This

additional ramp compensates for propagation time delays

from the current sense amplifier (CSA), the PWM

comparator and the MOSFET gate drivers. As a result, the

minimum ON time of the controller is reduced and lower

duty−cycles may be achieved at higher frequencies. Also,

the additional ramp reduces the reliance on the inductor

current ramp and allows greater flexibility when choosing

the output inductor and the RCSxCCSx time constant of the

feedback components from VCORE to the CSx pin.

Including both current and voltage information in the

feedback signal allows the open loop output impedance of

the power stage to be controlled. When the average output

current is zero, the COMP pin will be:

VCOMP + VOUT @0 A ) Channel_Startup_Offset

) Int_Ramp ) GCSA @ Ext_Ramp 2

Int_Ramp is the “partial” internal ramp value at the

corresponding duty cycle, Ext_Ramp is the peak−to−peak

external steady−state ramp at 0 A, GCSA is the current sense

amplifier gain (nominally 2.65 V/V) and the channel startup

offset is typically 0.60 V. The magnitude of the Ext_Ramp

can be calculated from:

Ext_Ramp + D @ (VIN * VOUT) (RCSx @ CCSx @ fSW)

For example, if VOUT at 0 A is set to 1.700 V with AVP

and the input voltage is 12.0 V, the duty cycle (D) will be

1.700/12.0 or 14.2%. Int_Ramp will be 115 mV/50% ⋅ 14.2%

= 33 mV. Realistic values for RCSx, CCSx and fSW are 10 kΩ,

0.015 μF and 650 kHz. Using these and the previously

mentioned formula, Ext_Ramp will be 15.0 mV.

VCOMP + 1.700 V ) 0.60 V ) 33 mV

) 2.65 V V @ 15.0 mV 2

+ 2.353 Vdc.

If the COMP pin is held steady and the inductor current

changes, there must also be a change in the output voltage.

Or, in a closed loop configuration when the output current

changes, the COMP pin must move to keep the same output

voltage. The required change in the output voltage or COMP

pin depends on the scaling of the current feedback signal and

is calculated as:

DV + RS @ GCSA @ DIOUT

The single−phase power stage output impedance is:

Single Stage Impedance + DVOUT DIOUT+RS @ GCSA

The total output impedance will be the single stage

impedance divided by 4.

The output impedance of the power stage determines how

the converter will respond during the first few microseconds

of a transient before the feedback loop has repositioned the

COMP pin.

The peak output current can be calculated from:

IOUT,PEAK + (VCOMP * VOUT * Offset) (RS @ GCSA)

Figure 15 shows the step response of the COMP pin at a

fixed level. Before T1, the converter is in normal

steady−state operation. The inductor current provides a

portion of the PWM ramp through the current sense

amplifier. The PWM cycle ends when the sum of the current

ramp, the “partial” internal ramp voltage signal and offset

exceed the level of the COMP pin. At T1, the output current

increases and the output voltage sags. The next PWM cycle

begins and the cycle continues longer than previously while

the current signal increases enough to make up for the lower

voltage at the VFB pin and the cycle ends at T2. After T2, the

output voltage remains lower than at light load and the

average current signal level (CSx output) is raised so that the

sum of the current and voltage signal is the same as with the

original load. In a closed loop system, the COMP pin would

move higher to restore the output voltage to the original

level.

SWNODE

VFB (VOUT)

Internal Ramp

CSA Out w/

Exaggerated

Delays

COMP−Offset

CSA Out + Ramp + CSREF

Figure 15. Open Loop Operation

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