Z86L71 datasheet(42/61 Pages) ZILOG

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Z86L70/71/75/C71

IR/Low-Voltage Microcontroller

Zilog

1-42

P R E L I M I N A R Y

DS97LVO0500

FUNCTIONAL DESCRIPTION (Continued)

HALT. HALT turns off the internal CPU clock, but not the

XTAL oscillation. The counter/timers and external inter-

rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.

The devices are recovered by interrupts, either externally

or internally generated. An interrupt request must be exe-

cuted (enabled) to exit HALT Mode. After the interrupt ser-

vice routine, the program continues from the instruction af-

ter the HALT.

STOP. This instruction turns off the internal clock and ex-

ternal crystal oscillation and reduces the standby current

to 10

µA or less. STOP Mode is terminated only by a reset,

such as WDT time-out, POR, SMR, or external reset. This

causes the processor to restart the application program at

address 000CH. In order to enter STOP (or HALT) mode,

it is necessary to first flush the instruction pipeline to avoid

suspending execution in mid-instruction. To do this, the

user must execute a NOP (opcode = FFH) immediately be-

fore the appropriate sleep instruction, i.e.,

NOP

; clear the pipeline

STOP

; enter STOP Mode

NOP

; clear the pipeline

HALT

; enter HALT Mode

Port Configuration Register (PCON). The PCON regis-

ter configures the comparator output on Port 3. It is locat-

ed in the expanded register file at Bank F, location 00 (Fig-

ure 32).

Figure 32. Port Conﬁguration Register (PCON)

(Write Only)

Reserved (Must be 1)

D4 D3

PCON (FH) 00H

Comparator Output Port 3

0 P34,Standard Output*

1 P34,Comparator Output

* Default Setting After Reset

Z86L71 Datasheet(PDF) 42 Page - Zilog, Inc.

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