SAFC505 datasheet(49/85 Pages) INFINEON

49 / 85 page

C505L

Data Sheet

06.99

Fail Save Mechanisms

The C505L offers enhanced fail safe mechanisms, which allow an automatic recovery from software

upset or hardware failure:

– a programmable watchdog timer (WDT), with variable time-out period from 192

µsupto

approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).

– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for

a fast internal reset after power-on.

The watchdog timer in the C505L is a 15-bit timer, which is incremented by a count rate of

OSC/12

up to

OSC/192. The system clock of the C505L is divided by two prescalers, a divide-by-two and a

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the

watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.

Figure 24

Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped

during active mode of the device. If the software fails to refresh the running watchdog timer an

internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the

content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog timer. The refresh

sequence consists of two consecutive instructions which set the bits WDT and SWDT each. The

reset cause (external reset or reset caused by the watchdog) can be examined by software (flag

WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and

power down mode of the processor.

MCB03306

IP0 (A9 )

OSC

WDTS

WDTL

WDTH

/ 6

External HW Reset

Control Logic

IEN0 (A8 )

IEN1 (B8 )

WDT Reset - Request

WDTPSEL

WDTREL (86 )

WDT

SWDT

OWDS

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