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RF430CL331HIPWR Datasheet(PDF) 38 Page - Texas Instruments |
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RF430CL331HIPWR Datasheet(HTML) 38 Page - Texas Instruments |
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38 / 60 page  RF430CL331H SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015 www.ti.com 5.11.3 Interrupt Registers The interrupt enable register (see Table 5-14 and Table 5-15) determines which interrupt events are signaled on the external output pin INTO. Setting any bit high in this register allows the corresponding event to trigger the interrupt signal. See Table 5-18 for a description of each interrupt. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. Table 5-14. Interrupt Enable Register ADDRESS 15 14 13 12 11 10 9 8 Read 0xFFFB Reserved Prefetch ADDRESS 7 6 5 4 3 2 1 0 CRC RF Field General Type BIP-8 Error 0xFFFA Generic Error Calculation Reserved Removed 4 Request Detected Completed Table 5-15. Interrupt Enable Register Description BIT FIELD TYPE RESET DESCRIPTION 15-9 Reserved R 0 Reserved for future use. Write with 0. Enable for the Read Prefetch IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 8 Read Prefetch R/W 0 0b = IRQ disabled 1b = IRQ enabled Enable for the Generic Error IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 7 Generic Error R/W 0 0b = IRQ disabled 1b = IRQ enabled Enable for the RF Field Removed IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 6 RF Field Removed R/W 0 0b = IRQ disabled 1b = IRQ enabled Enable for the General Type 4 Request IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 5 General Type 4 Request R/W 0 0b = IRQ disabled 1b = IRQ enabled Enable for the BIP-8 Error Detected IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 4 BIP-8 Error Detected R/W 0 0b = IRQ disabled 1b = IRQ enabled Enable for the CRC Calculation Completed IRQ. All enabled interrupt signals are ORed together, and the result is signaled on the output pin INTO. 3 CRC Calculation Completed R/W 0 0b = IRQ disabled 1b = IRQ enabled 2-0 Reserved R 0 Reserved for future use. Write with 0. 38 Detailed Description Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: RF430CL331H |
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