RM41L232 datasheet(6/108 Pages) TI1

6 / 108 page

RM41L232

SPNS240A – OCTOBER 2014 – REVISED JUNE 2015

www.ti.com

Table of Contents

Device Overview

......................................... 1

6.9

Flash Memory

....................................... 49

6.10

Flash Program and Erase Timings for Program

1.1

Features

.............................................. 1

Flash

................................................ 51

1.2

Applications

........................................... 2

6.11

Flash Program and Erase Timings for Data Flash

.. 51

1.3

Description

............................................ 3

6.12

Tightly Coupled RAM Interface Module

............. 52

1.4

Functional Block Diagram

............................ 5

6.13

Parity Protection for Accesses to peripheral RAMs

. 52

Revision History

......................................... 7

6.14

On-Chip SRAM Initialization and Testing

........... 53

Device Comparison

..................................... 8

6.15

Vectored Interrupt Manager

......................... 55

Terminal Configuration and Functions

............. 9

6.16

Real-Time Interrupt Module

......................... 57

4.1

PZ QFP Package Pinout (100-Pin)

................... 9

6.17

Error Signaling Module

.............................. 58

4.2

Terminal Functions

................................. 10

6.18

Reset / Abort / Error Sources

....................... 62

4.3

Output Multiplexing and Control

..................... 16

6.19

Digital Windowed Watchdog

........................ 63

4.4

Special Multiplexed Options

......................... 17

6.20

Debug Subsystem

................................... 64

Specifications

.......................................... 18

Peripheral Information and Electrical

5.1

Absolute Maximum Ratings

......................... 18

Specifications

........................................... 69

5.2

ESD Ratings

........................................ 18

7.1

Peripheral Legend

................................... 69

5.3

Power-On Hours (POH)

............................. 18

7.2

Multibuffered 12-Bit Analog-to-Digital Converter

.... 69

5.4

Recommended Operating Conditions

............... 19

7.3

General-Purpose Input/Output

...................... 77

5.5

Switching Characteristics Over Recommended

7.4

Enhanced High-End Timer (N2HET)

................ 78

Operating Conditions for Clock Domains

........... 19

7.5

Controller Area Network (DCAN)

.................... 81

5.6

Wait States Required

............................... 20

7.6

Local Interconnect Network Interface (LIN)

......... 82

5.7

Power Consumption

................................ 21

7.7

Multibuffered / Standard Serial Peripheral Interface

5.8

Thermal Resistance Characteristics for PZ

......... 22

7.8

Enhanced Quadrature Encoder (eQEP)

............ 93

5.9

Input/Output Electrical Characteristics

.............. 22

Device and Documentation Support

............... 95

5.10

Output Buffer Drive Strengths

...................... 23

8.1

Device Support

...................................... 95

5.11

Input Timings

........................................ 24

8.2

Documentation Support

............................. 97

5.12

Output Timings

...................................... 25

8.3

Community Resources

.............................. 97

System Information and Electrical

Specifications

........................................... 27

8.4

Trademarks

.......................................... 97

6.1

Voltage Monitor Characteristics

..................... 27

8.5

Electrostatic Discharge Caution

..................... 97

6.2

Power Sequencing and Power-On Reset

........... 28

8.6

Glossary

............................................. 97

6.3

Warm Reset (nRST)

................................. 30

8.7

Device Identification Code Register

................. 97

6.4

ARM Cortex-R4 CPU Information

................... 31

8.8

Die Identification Registers

......................... 98

6.5

Clocks

............................................... 35

8.9

Module Certifications

................................ 99

6.6

Clock Monitoring

.................................... 41

Mechanical Packaging and Orderable

Addendum

.............................................. 104

6.7

Glitch Filters

......................................... 43

9.1

Packaging Information

............................. 104

6.8

Device Memory Map

................................ 44

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