 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AT90LS4433-4AI Datasheet(PDF) 82 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
AT90LS4433-4AI Datasheet(HTML) 82 Page - ATMEL Corporation |
|
|
82 / 126 page  82 AT90S/LS4433 1042H–AVR–04/03 •TXD – Port D, Bit 1 Transmit Data (Data Output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1. • RXD – Port D, Bit 0 Receive Data (Data Input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regardless of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up. Port D Schematics Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 57. Port D Schematic Diagram (Pin PD0) D D Q Q RESET RESET C C WD WP RD MOS PULL- UP PD0 RXD RXEN WP: WD: RL: RP: RD: RXD: RXEN: WRITE PORTD WRITE DDRD READ PORTD LATCH READ PORTD PIN READ DDRD UART RECEIVE DATA UART RECEIVE ENABLE DDD0 PORTD0 RL RP |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
