ADuC7122BBCZ datasheet(7/96 Pages) AD

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Data Sheet

ADuC7122

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

FLASH/EE MEMORY

Endurance11

10,000

Cycles

Data Retention12

Years

TJ = 85°C

DIGITAL INPUTS

All digital inputs excluding XTALI and XTALO

Logic 1 Input Current

±0.2

±1

µA

VIH = VDD or VIH = 5 V

Logic 0 Input Current

−40

−60

µA

VIL = 0 V; except TDI

Input Capacitance

LOGIC INPUTS4

All logic inputs excluding XTALI

VINL, Input Low Voltage4

0.8

VINH, Input High Voltage4

2.0

LOGIC OUTPUTS

All digital outputs excluding XTALO

VOH, Output High Voltage

2.4

ISOURCE = 1.6 mA

VOL, Output Low Voltage13

0.4

ISINK = 1.6 mA

CRYSTAL INPUTS XTALI and XTALO

Logic Inputs, XTALI Only

VINL, Input Low Voltage

1.1

VINH, Input High Voltage

1.7

XTALI Input Capacitance

XTALO Output Capacitance

INTERNAL OSCILLATOR

32.768

kHz

±3

MCU CLOCK RATE

From 32 kHz Internal Oscillator

326

kHz

CD = 7

From 32 kHz External Crystal

41.78

MHz

CD = 0

Using an External Clock

0.05

41.78

MHz

TA = 95°C

START-UP TIME

Core clock = 41.78 MHz

At Power-On

From Pause/Nap Mode

CD = 0

3.06

µs

CD = 7

From Sleep Mode

1.58

From Stop Mode

1.7

PROGRAMMABLE LOGIC ARRAY (PLA)

Pin Propagation Delay

From input pin to output pin

Element Propagation Delay

2.5

POWER REQUIREMENTS14, 15

Power Supply Voltage Range

AVDD to AGND and IOVDD to IOGND

3.0

3.6

Analog Power Supply Currents

AVDD Current

200

µA

ADC in idle mode

Digital Power Supply Current

IOVDD Current in Normal Mode

Code executing from Flash/EE

CD = 7

CD = 3

CD = 0 (41.78 MHz clock)

IOVDD Current in Pause Mode4

CD = 0 (41.78 MHz clock)

IOVDD Current in Sleep Mode4

100

µA

TA = 85°C

Additional Power Supply Currents

ADC

2.7

At 1 MSPS

DAC

250

µA

Per DAC

Rev. A | Page 7 of 96

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