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Z80 Datasheet(PDF) 78 Page - Zilog, Inc. |
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Z80 Datasheet(HTML) 78 Page - Zilog, Inc. |
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78 / 330 page  <%27 2GTKRJGTCNU 7UGT /CPWCN UM008101-0601 Direct Memory Access Auto Restart Block transfers can be repeated automatically by the DMA. This function causes the byte counter to be cleared and the address counters to be reloaded with the contents of the starting-address registers. The Auto Restart feature relieves the CPU of software overhead for repet- itive operations such as CRT refresh and many others. Moreover, the CPU can write different starting addresses into the buffer registers during transfers in the Byte mode (or Burst mode when the Ready line is inactive and the bus is released) causing the Auto Restart to begin at a new location. Pulse Generation External devices can keep track of how many bytes have been transferred by using the DMA’s Pulse output, which provides a signal at 256-byte intervals. The interval sequence may be offset at the beginning by 1 to 255 bytes. The interrupt line carries the Pulse signal in a manner that prevents inter- pretation by the Z80 CPU as an interrupt request, because the signal only appears when the Bus Request and Bus Acknowledge lines are both active. Under these conditions, the Z80 CPU does not monitor the Interrupt (INT) line. Variable Cycle The Z80 DMA offers the unique feature of programmable operation-cycle length. This is valuable in tailoring the DMA to the particular requirements of various CPUs and other system components (fast or slow), and in maxi- mizing the data-transfer rate. Also, it often eliminates external logic and reduces CPU software overhead. There are two aspects to the variable cycle feature. First, the entire read and write cycles (periods) associated with the source and destination ports can |
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