|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||

2013-06-0002

PT0205-9

06/18/13

10

PT7C4337

Real-time Clock Module (I

Square wave frequency selection bits



RS2, RS1

Square wave Rate Select. These bits control the frequency of the square-wave output when the square wave has been enabled.

RS2, RS1

Data

SQW output freq. (Hz)

Read / Write

00

1

01

4.096k

10

8.192k

11

32.768k

Default

Interrupt related bits



INTCN

Interrupt Output pin select bit. This bit controls the relationship between the two alarms and the interrupt output pins.

INTCN

Data

Description

Read /

Write

1

A match between the timekeeping registers and the alarm 1 registers activates the INTA pin (if the

alarm 1 is enabled) and a match between the timekeeping registers and the alarm 2 registers activates

the SQW/INTB pin (if the alarm 2 is enabled).

0

A match between the timekeeping registers and either alarm 1 or alarm 2 registers activates

the INTA pin (if the alarms are enabled). In this configuration, a square wave is output on

the SQW/INTB pin.

Default



A1IE

Alarm 1 Interrupt Enable.

A1IE

Data

Description

Read /

Write

0

The A1F bit does not initiate the INTA signal.

Default

1

Permits the alarm 1 flag (A1F) bit in the status register to assert INTA.



A1F

Alarm 1 Flag.

A1F

Data

Description

Read / Write

0

The time do not match the alarm 1 registers.

Default

Read

1

Indicates that the time matched the alarm 1 registers. If the A1IE bit is also logic 1, the INTA pin goes

low. A1F is cleared when written to logic 0. Attempting to write to logic 1 leaves the value unchanged.



A2IE

Alarm 2 Interrupt Enable.

A2IE

Data

Description

Read /

Write

0

The A2F bit does not initiate an interrupt signal.

Default

1

Permits the alarm 2 flag (A2F) bit in the status register to assert INTA (when INTCN = 0) or to assert

SQW/INTB (when INTCN = 1).