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PT7C4337 Datasheet(PDF) 17 Page - Pericom Semiconductor Corporation

Part # PT7C4337
Description  Real-time Clock Module
PDF  23 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PT7C4337 Datasheet(HTML) 17 Page - Pericom Semiconductor Corporation

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2013-06-0002
PT0205-9
06/18/13
17
PT7C4337
Real-time Clock Module (I
2C Bus)
Starting and Stopping I
2C Bus Communications
Fig 2. Starting and stopping on I
2C bus
1) START condition, repeated START condition, and STOP condition
a) START condition
SDA level changes from high to low while SCL is at high level
b) STOP condition
SDA level changes from low to high while SCL is at high level
c) Repeated START condition (RESTART condition)
In some cases, the START condition occurs between a previous START condition and the next STOP condition, in
which case the second START condition is distinguished as a RESTART condition. Since the required status is the same as for the
START condition, the SDA level changes from high to low while SCL is at high level.
2) Data Transfers and Acknowledge Responses during I
2C-BUS Communication
a)
Data transfers
Data transfers are performed in 8-bit (1 byte) units once the START condition has occurred. There is no limit on the amount
(bytes) of data that are transferred between the START condition and STOP condition.
The address auto increment function operates during both write and read operations.
Updating of data on the transmitter (transmitting side)'s SDA line is performed while the SCL line is at low level.
The receiver (receiving side) captures data while the SCL line is at high level.
*Note with caution that if the SDA data is changed while the SCL line is at high level, it will be treated as a START, RESTART,
or STOP condition.
b)
Data acknowledge response (ACK signal)
When transferring data, the receiver generates a confirmation response (ACK signal, low active) each time an 8-bit data segment
is received. If there is no ACK signal from the receiver, it indicates that normal communication has not been established. (This
does not include instances where the master device intentionally does not generate an ACK signal.)
Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line, the transmitter releases
the SDA line and the receiver sets the SDA line to low (= acknowledge) level.



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