IS25LP032 datasheet(28/90 Pages) ISSI

28 / 90 page

IS25LP032/064/128

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

10/03/2014

8.5 FAST READ DUAL OUTPUT OPERATION (FRDO, 3Bh)

The FRDO instruction is used to read memory data on two output pins each at up to a 133MHz clock.

The FRDO instruction code is followed by three address bytes (A23

– A0) and a dummy byte (8 clocks),

transmitted via the SI line, with each bit

latched-in during the rising edge of SCK. Then the first data byte addressed is shifted out on the SO and SIO lines,

with each pair of bits shifted out at a maximum frequency fCT, during the falling edge of SCK. The first bit (MSB) is

output on SO, while simultaneously the second bit is output on SIO.

The first byte addressed can be at any memory location. The address is automatically incremented by one after

each byte of data is shifted out. When the highest address is reached, the address counter will roll over to the

000000h address, allowing the entire memory to be read with a single FRDO instruction. The FRDO instruction is

terminated by driving CE# high (VIH). If the FRDO instruction is issued while an Erase, Program or Write cycle is in

process (BUSY=1) the instruction is ignored and will not have any effects on the current cycle.

IS25LP032 Datasheet(PDF) 28 Page - Integrated Silicon Solution, Inc