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IS25LP032 Datasheet(PDF) 38 Page - Integrated Silicon Solution, Inc |
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IS25LP032 Datasheet(HTML) 38 Page - Integrated Silicon Solution, Inc |
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38 / 90 page ![]() IS25LP032/064/128 Integrated Silicon Solution, Inc.- www.issi.com 38 Rev. D 10/03/2014 8.11 BLOCK ERASE OPERATION (BER32K:52h, BER64K:D8h) A Block Erase (BER) instruction erases a 32/64 Kbyte block of the IS25LP032/064/128. Before the execution of a BER instruction, the Write Enable Latch (WEL) must be set via a Write Enable (WREN) instruction. The WEL is reset automatically after the completion of a block erase operation. The BER instruction code and three address bytes are input via SI. Erase operation will start immediately after the CE# is pulled high, otherwise the BER instruction will not be executed. The internal control logic automatically handles the erase voltage and timing. Refer to Figure 8.14-8.17 for the Block Erase Sequence. Figure 8.14 Block Erase (64k) Sequence Instruction = D8h 23 CE # SCK SI 3 2 SO 1 0 3-byte Address High Impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 Mode 3 Mode 0 Figure 8.15 Block Erase (64k) Sequence (QPI) D8h CE# SCK IO[3:0] Address 0 1 2 3 4 5 6 7 Mode 3 Mode 0 23:20 19:16 15:12 11:8 7:4 3:0 |
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