IS25LP032 datasheet(67/90 Pages) ISSI

67 / 90 page

IS25LP032/064/128

Integrated Silicon Solution, Inc.- www.issi.com

Rev. D

10/03/2014

Figure 8.52 FRDDTR (Fast Read Dual IO DTR Mode) OPERATION (with command decode cycles)

CE #

SCK

Instruction = BDh

CE #

SCK

3-byte Address

High Impedance

...

Mode 3

Mode 0

...

22 20 18

7 5 3 1 7

5 3

1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1

2 Dummy Cycles

23 21 19

Data Out

...

6 4 2 0 6

4 2

0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

Data Out

...

16 14 12

17 15 13

7 5

6 4

3 1

2 0

Mode Bits

Notes:

1. If the mode bits=AXh (X:

don’t care), it can execute the AX read mode (without command). When the mode bits

are different from

AXh (X is don’t care), the device exits the AX read operation.

2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.9 Read Dummy Cycles.

3. Since the number of dummy cycles and AX bits cycles are same in the above Figure, X should be Hi-Z to avoid

I/O contention.

IS25LP032 Datasheet(PDF) 67 Page - Integrated Silicon Solution, Inc

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