BCM4354 datasheet(75/192 Pages) CYPRESS

75 / 192 page

PCI Express Interface

BCM4354 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

October 15, 2014 • 4354-DS109-R

Page 74

Electrical Subblock

The high-speed signals utilize the Common Mode Logic (CML) signaling interface with on-chip termination and

de-emphasis for best-in-class signal integrity. A de-emphasis technique is employed to reduce the effects of

Intersymbol Interference (ISI) due to the interconnect by optimizing voltage and timing margins for worst case

channel loss. This results in a maximally open “eye” at the detection point, thereby allowing the receiver to

receive data with acceptable Bit-Error Rate (BER).

To further minimize ISI, multiple bits of the same polarity that are output in succession are de-emphasized.

Subsequent same bits are reduced by a factor of 3.5 dB in power. This amount is specified by PCIe to allow for

maximum interoperability while minimizing the complexity of controlling the de-emphasis values. The high-

speed interface requires AC coupling on the transmit side to eliminate the DC common mode voltage from the

receiver. The range of AC capacitance allowed is 75 nF to 200 nF.

Configuration Space

The PCIe function in the BCM4354 implements the configuration space as defined in the PCI Express Base

Specification v3.0

BCM4354 Datasheet(PDF) 75 Page - Cypress Semiconductor