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BCM4354 Datasheet(PDF) 169 Page - Cypress Semiconductor |
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BCM4354 Datasheet(HTML) 169 Page - Cypress Semiconductor |
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169 / 192 page  SDIO Timing BCM4354 Data Sheet BROADCOM CONFIDENTIAL Broadcom® October 15, 2014 • 4354-DS109-R Page 168 Table 51: SDIO Bus Timinga Parameters (Default Mode) a. Timing is based on CL 40pF load on CMD and Data. Parameter Symbol Minimum Typical Maximum Unit SDIO CLK (All values are referred to minimum VIH and maximum VILb) b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO. Frequency – Data Transfer mode fPP 0 – 25 MHz Frequency – Identification mode fOD 0 – 400 kHz Clock low time tWL 10 – – ns Clock high time tWH 10 – – ns Clock rise time tTLH – – 10 ns Clock low time tTHL – – 10 ns Inputs: CMD, DAT (referenced to CLK) Input setup time tISU 5––ns Input hold time tIH 5––ns Outputs: CMD, DAT (referenced to CLK) Output delay time – Data Transfer mode tODLY 0 – 14 ns Output delay time – Identification mode tODLY 0 – 50 ns |
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